Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and lengths of interconnections between devices as the number of devices increases. When the number and the lengths of interconnections increase, both circuit RC delay and power consumption increase.
Among the efforts for resolving the above-discussed limitations, three-dimensional integrated circuits (3DICs) and stacked dies are commonly used. Through-silicon vias (TSVs) are thus used in 3DIC and stacked dies for connecting dies. In this case, TSVs are often used to connect the integrated circuits on a die to the backside of the die. In addition, TSVs are also used to provide short grounding paths for grounding the integrated circuits through the backside of the die, which may be covered by a grounded metallic film.
FIG. 1 illustrates a conventional TSV 102 formed in chip 104. TSV 102 is in silicon substrate 106. Through the interconnections (metal lines and vias, not shown) in the metallization layers, TSV 102 is electrically connected to bond pad 108, which is on the front surface of chip 104. TSV 102 is exposed through the back surface of substrate 106 in the form of a copper post. When chip 104 is bonded to another chip, TSV 102 is bonded to a bond pad on the other chip, with or without solder therebetween. This scheme suffers from drawbacks. Since the TSV bonding requires relatively large pitch between TSVs, the location of the TSVs are restricted and the distance between the TSVs needs to be big enough to allow room for, for example, solder balls. New backside structures are thus needed.